FSINVEN=DISABLED, DDIS=INACTIVE, JSEL=LEFT, ORDER=LEFT_RIGHT, FSSRCSEL=FSIN_EXT, SCLKINVEN=DISABLED, RXEN=DISABLED, MBSEL=8BITS
Receive Control
| FSDEL | Receive Initial Phase Delay. |
| JSEL | Receive Data Justification. 0 (LEFT): Use left-justified or I2S-style formats. 1 (RIGHT): Use right-justified format. |
| DDIS | Receive Delay Disable. 0 (INACTIVE): The first data bit is captured on the second or later rising edge of SCK after WS changes. 1 (ACTIVE): The first data bit is captured by the receiver on the first rising edge of SCK after WS changes. |
| FSINVEN | Receive WS Inversion Enable. 0 (DISABLED): Don’t invert the WS signal. Use this setting for I2S format. 1 (ENABLED): Invert the WS signal. |
| SCLKINVEN | Receive SCK Inversion Enable. 0 (DISABLED): Do not invert the receiver bit clock. 1 (ENABLED): Invert the receiver bit clock. |
| ORDER | Receive Order. 0 (LEFT_RIGHT): Left sample received first, right sample received second. Use this setting for I2S format. 1 (RIGHT_LEFT): Right sample received first, left sample received second. |
| MBSEL | Receive Mono Bit-Width Select. 0 (8BITS): 8 bits are received per mono sample. 1 (9BITS): 9 bits are received per mono sample. 2 (16BITS): 16 bits are received per mono sample. 3 (24BITS): 24 bits are received per mono sample. 4 (32BITS): 32 bits are received per mono sample. |
| FSSRCSEL | Receive Frame Sync Source Select. 0 (FSIN_EXT): The word select or frame sync is input from the WS pin. 1 (FSIN_INT): The word select or frame sync is input from the internal DFS generator. |
| RXEN | Receive Enable. 0 (DISABLED): Disable the I2S receiver. 1 (ENABLED): Enable the I2S receiver. |